The present invention relates generally to memory controllers for controlling and managing access to dynamic memory devices, and particularly to power management logic for enabling the memory controller to maximize memory performance while keeping total energy usage within a predefined budget or minimized (e.g., for battery-operated systems).
The main memory of a computer, mobile device, or other computer controlled system may be populated by a number of DRAM (dynamic random access memory) devices, such as Rambus xe2x80x9cDirect RDRAMxe2x80x9d devices. In some applications there is a need to limit the amount of power drawn by the memory devices, either to conserve power, limit thermal heat dissipation, or both. Many DRAM devices, including Rambus Direct RDRAM devices, support multiple modes of operation, each with a distinct performance/power/latency characteristic. Lower power states are typically characterized by higher latencies, because of the time required for the memory device to return from the low power state to a normal mode of operation. Table 1 lists states, power consumed in each state, and the corresponding latency to exit the state (and thus to return to the Active state), for a typical Direct RDRAM device, circa 2000.
In some non-portable system configurations with adequate cooling, power management may not be required, and all the DRAM devices not currently being accessed could be kept in the Active Idle state.
A dynamic random access memory (DRAM) contains an array of storage elements, often called memory cells, each storing one bit of data. At the lowest level, these elements are organized into rows and columns, where one row may be accessed at a time. From the row, certain columns are selected to perform a read or write operation.
Referring to FIG. 1, a single DRAM device 100 may contain multiple internal storage arrays organized as banks 102. A bank 102 is a storage array 104 and its associated sense amp (sense amplifier) arrays 106. The memory array in a 64 Mbit Rambus DRAM (RDRAM) typically contains 16 banks. Each unique device, bank, and row combination is called a page.
Banks in a DRAM can be independent or dependent. Independent banks each have their own sense amp arrays, independent of all other banks. Each bank can operate independently of its adjacent banks.
An independent bank can be in one of two states: open or closed. An open bank has had the contents of one row transferred to a sense amp array, from where it may be rapidly accessed by a so-called column operation. Access to a closed bank requires a row operation to transfer the contents of the desired row to the sense amp cache before the column operation, and is much slower than access to an open bank.
Referring to FIG. 2, there is shown a DRAM device 110 having dependent banks 112. As shown, dependent banks share adjacent sense amp arrays 114. For instance, neighbor banks n and n+1 share the sense amp array positioned between the DRAM cell arrays for those two banks. This reduces the area occupied by sense amplifiers because only N+1 sense amp arrays are required, instead of the 2N sense amp arrays used in the device of FIG. 1, where N is the number or banks. But because it shares sense amp arrays with adjacent banks (called neighbor banks or just neighbors), a dependent bank cannot operate independently of its neighbors. When a dependent bank accesses its sense amp arrays, its neighbors must be closed.
A dependent bank that is closed and has a neighbor open is said to be locked. Locked banks cannot be opened until all neighbor banks are closed. As a convenience, the DRAM""s internal logic is arranged so that a precharge operation on any locked bank will also close any open neighbor banks. In other words, whenever a bank is precharged, its associated sense amps are precharged. If neighbor banks are open, their sense amps are precharged as well. If the locked bank is an edge bank at the end of the bank array, up to three sense amp arrays may be precharged, and otherwise up to four sense amp arrays may be precharged. A locked bank can be accessed by a precharge operation, a row operation, and then a column operation.
Still referring to FIG. 2, a bank set is a set of two or three dependent banks. The banks at each end in a DRAM device having a dependent bank organization form a bank set with two banks, because they do not share one of their sense amp arrays. All other banks in the DRAM device must form a bank set with three banks, because they share both associated sense amp arrays.
The present invention provides a memory controller apparatus and method to control a set of DRAM devices. Each DRAM device may be composed of several dependent banks. Among other tasks, the memory controller is responsible for its managing and tracking the state of each bank in the system: open, closed, or (for dependent banks only) locked. From a general perspective, two types of bank control policies that a memory controller could use for managing the bank state of the banks in a multiple bank DRAM are open-page and closed-page.
The closed-page policy is to close (i.e., precharge) the bank used in a memory access operation after every access. This is simplest because there is no need to track the state of any banks other than those being used in memory access operations that have not yet finished. If a bank is not being used, it is closed.
The open-page policy would leave each page (i.e., row of a bank) open as long as possible. If subsequent requests frequently select the same page (this is the case for many applications) row operations are avoided and performance is improved. How long the page can be left open is limited by two factors: bank dependencies (only one page may be open in a bank at a time, and a dependent bank must be closed before opening its neighbor) and the ability of the memory controller to track which banks are open.
A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Depending on the memory devices, the number of possible power states will vary, but will generally includes at least a first (active) state, a second (mid-power) state, and a third (low power) state, where the second power state uses less power than the first power state, and the third power state uses less power than the second. The cache entries include, at most, a second predefined maximum number of entries specifying dynamic memory devices in the second, mid-power state. The cache entries may also include, at most a first predefined maximum number of entries specifying dynamic memory devices in the first power state (e.g., the Active state). Alternately stated, a first subset of the memory devices are assigned to a first pool (herein called the xe2x80x9cactive poolxe2x80x9d) having no more than the first predefined number of devices and a second subset of the memory devices are assigned to a second pool (xe2x80x9cthe standby pool) having no more than the second predefined number of devices. The first and second pools correspond to the Active and mid-power states of the memory devices. All memory devices not assigned to the active and standby pools are assigned to a low power (nap) state.
Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves fullness information indicating whether the active pool is full and whether the standby pool is full.
Additional logic converts the first information, fullness information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal. Command issue circuitry issues power state commands and access commands to the dynamic memory devices in accordance with the at least one command selection signal and the address in the memory access request.